LTE (Long Term Evolution), one of the wireless industry's 4G solutions rolling out over the next several years, presents a series of lofty goals. These goals create a difficult set of challenges to technology providers, equipment manufacturers and service providers.
LTE is the next-generation of the 3G Universal Mobile Telecommunication System (UMTS) wireless protocol. It is being developed by the Third Generation Partnership Project (3GPP) with the aim of moving cellular toward a packet-based all-IP (Internet Protocol) network. Among the goals of LTE are significantly higher download and upload data rates (100 and 50 megabits per second (Mbps) respectively), and low packet latencies, which are no more than five milliseconds (ms). The latter is increasingly critical for new services such as wireless voice-over-IP (VoIP). For good measure, the technology must also offer greater spectrum efficiency, increased capacity and reduced cost per bit communicated.
LTE reaches these goals by using several concepts that add significantly to the complexity of the technology. These include, among other leading-edge techniques, more complex modulation schemes in the download and upload directions, flexible channel bandwidths, and a Multiple Input/Multiple Output (MIMO) architecture which in some cases, requires multiple antennas. Ultimately, the increased complexity in LTE will require very powerful, flexible and innovative processing in base stations and handsets.
LTE implements the orthogonal frequency division multiplex (OFDM) modulation scheme in the downlink direction and an OFDM-derivative, single-carrier frequency division multiple access (SC-FDMA), in the uplink. SC-FDMA is used for uplink because it offers greater power amplifier efficiency than OFDM, which translates into longer battery life for handsets. OFDM is rather complex, incorporating 2,048 sub-carriers with a 15 Khz spacing. This high number of sub-carriers enhances OFDM's multi-path capabilities, which strengthens its resistance to interference, improves spectral efficiencies and increases data rates.
Scalable bandwidths that scale from 1.25 to 20 MHz in both the downlink and uplink directions allow LTE to use both new and existing frequency bands. A MIMO architecture helps LTE achieve its high data rates through multiple signal paths. But here again, LTE implements slightly different schemes for downloads and uploads in order to control costs in LTE handsets. MIMO has the potential to increase data rates beyond 100/50 Mbps if handsets are equipped with multiple antennas.
Equipping LTE Base Stations
To address the high level of complexity in LTE, TI has developed the TCI6487 multicore DSP with embedded accelerators for 2G, 3G and 4G wireless base station standards that are used in baseband processing. The TCI6487 is the industry's first multi-core digital signal processor (DSP) that has three 'C64+ DSP cores' and provides a total of 3 Gigahertz (GHz) of DSP processing power with which to tackle LTE baseband tasks such as MAC and PHY processing.
To achieve LTE's higher data rates and ensure packet latencies of less than 5 ms, the device includes a Viterbi and a Turbo Co-Processor (TCP) to offload the coding/decoding burden from the main DSP cores. These co-processing accelerators handle much of the mathematically-intense coding functions needed in LTE processing. Specifically, the TCP2 was developed as a flexible accelerator to support Turbo Decoding; it can support not only LTE but also all 3GPP family of standards. Offloading the Turbo decoding from the TCI6487's DSP cores frees up processing capacity for MAC and PHY processing. Or, alternately, the available processing headroom can be deployed to process more users in base stations in particularly dense cells.
A certain level of flexibility and re-configurability is critical if a base station is to meet the higher requirements of LTE. For example, in a low density cell, the TCI6487 could be deployed as a one-chip solution with one core dedicated to MAC processing and the other two performing PHY level transmit and receive functions. High-density cells with many users taking advantage of LTE's higher data rates present a different set of challenges. In this case, multiple TCI6487s might be deployed with one chip performing all of the cell's MAC processing and the other devices handling PHY transmit and receive tasks. In this way, DSPs could be dedicated to either the OFDM or the SC-FDMA modulation schemes implemented in the LTE download and upload modes.
A multi-level on-chip memory architecture is required to capitalize on the flexibility inherent in a multi-core device. With the TCI6487, level 1 (L1) memory can be configured as either cache or standard memory storage. In addition, the amount of L2 memory devoted to each core is partially scalable. The total of 3 MB of L2 memory can be split evenly between the three cores, or the three cores could be assigned 0.5, 1 and 1.5 MB each. This can affect the efficiency of a complex LTE deployment where several distinct processing needs are ongoing at the same time. For example, a core that is processing a memory-intense task might be configured with 1.5 MB of L2 memory.
Keeping up with LTE
To avoid bottlenecks, transferring data through a base station at LTE rates requires very high-speed I/O for moving data into and out of the DSPs. As a result, the peripherals on the TCI6487 include the Serial Rapid IO (SRIO) interface. SRIO extends the flexibility and scalability of the device to the board level, lowering board complexities and costs.
The two-lane SRIO interface is capable of data rates of 1.25, 2.5 or 3.125 gigabits per second (Gbps) on each lane. It is configured as a two single-lane high-speed dedicated links between devices such as ASICs or FPGAs on the circuit board or among boards in an LTE base station backplane.
In another configuration, SRIO could interconnect multiple DSPs in a peer-to-peer arrangement or in a master/slave architecture. When configured as on-board peer-to-peer connections between chips, the dedicated SRIO lanes can eliminate the bottleneck problems that shared buses run into when they become overloaded. With the huge amounts of data that LTE is capable of transferring, this can become very critical. The scalability and flexibility of the SRIO interface enables a wide variety of architectures, including a star, ring, U-shaped daisy chain and others.
Another option for chip-to-chip interconnects on LTE base station cards is a Gigabit Ethernet switch fabric. To enable this, the TCI6487 also incorporates a Gigabit Ethernet interface.
